Timex FDD Interface
A major contributor of this text seems to be Jaroslaw Adamski.
This is only a part of the information found on the web page located at http://217.97.12.194/curious/Hardware/fdd1.html
It is not clear who the author of the web page is, but much credit is given to Mr. Adamski for the contents.This version is edited for the TIMEXsinclair Showcase by Jack Boatwright.
TMX Portugal made two versions of the FDD interface: one version for the TC2048 computer (it can also be used with the TC2068 utilizing the Spectrum Emulator cartridge) and one version for the TC2068 (on this version, the reset button is silver. The rest of the Interface is the same). This is because the FDD Interface ROM initialization works jointly with the computer's ROM and the TC2048 and TC2068 (and TS2068) ROMs are not the same. If the correct version of the FDD Interface is not used with the computer it was designed for, the computer will crash.
The FDD Interface
The FDD and FDD-3000 systems communicate with the computer through the FDD Interface. The Interface has one connector for the computer's edge connector, and one connector for the FDD. You can use any type of FDD Interface with any type of FDD or FDD-3000. For ZX's with 128K, the FDD Interface requires special Eprom reprogramming due to a port conflict. Only FDD Interfaces from STAVI are free of that bug.
The FDD-3000 is connected to the FDD Interface through a spiral cable. Transfer is half duplex, 6 bit (1 bit is STROBE, all bits can be used normal) this gives low transfer rate.
The FDD interface is not a complex unit. Ports are accessible by out/in #EF.
Inside the FDD is it port #0F, AND MIRRORED: #2F,#4F,#6F,#8F,#AF,#CF,#EF.
PORTS ARE CONNECTED THIS WAY: (TI BIT n MEAN BIT in timex interface #ef) BIT READ WRITE NOTE
7 DREQ FDC 1772 ?
6 TI BIT 6 TI BIT 6
5 DREQ FDC 1772 ?
4 TI BIT 4 OR 7 TI BIT 4 OR 7 DEPENDS ON TI VERSION... STANDARD IS 4
3 TI BIT 3 TI BIT 3
2 TI BIT 2 TI BIT 2
1 TI BIT 1 TI BIT 1
0 TI BIT 0 TI BIT 0
The Interface also has a RESET switch, and an amplifier of the CV signal, which is accessible at the TIMEX FDD-3000 MONITOR output. It has a lot of interference (TTL signals in the spiral cable, no shielding, 1-meter long).
What is inside?
INSIDE FDD - PORTS, and SHORT diz PORT INSIDE CHIP STERRED WHAT DOES IT DO?
#10 WD2123 configuration (write) CHA
#11 WD2123 configuration (write) CHB
#40 WD2123 data CHB
#41 WD2123 status/command CHB
#80 WD2123 data CHA
#81 WD2123 status/command CHA
#C0 FDC1770 sterring port/status
#C1 FDC1770 track port
#C2 FDC1770 sector port
#C3 FDC1770 data port
#E0 HELPING helping port(below)
HOW TO USE TIZ PORTS? i still wait for info... but : PORT #E0
BIT WRITE 1 0
7 HEAD DOWN UP
6 #0000-#1FFF ROM RAM
5 DENSITY FM MFM
4 SIDE 1 0
3 DRIVE 3 ON OFF
2 DRIVE 2 ON OFF
1 DRIVE 1 ON OFF
0 DRIVE 0 ON OFF
Interface scructure.
The Interface looks like this:
On the top is a connector to the real FDD-3000/3; below it is RAM, below that the EPROM, and from the top right: two line buffers and 2 GAL's (dolny/gorny). On the bottom is the edge connector.
The description of the TIMEX INTERFACE, which is used to connect computer with a ZX SPECTRUM compatible edge connector to the TIMEX FDD-3000 or polbrit clones.
Interface decode addresses:
memory : #0000 and #0008 with _M1 active - disconnection of ZX ROM.
memory : #0604 with _M1 - reconection of ZX ROM
port #xxEF - input/output 8 bit.
After disconnection of ZX ROM interface connect its memory in these areas:
#0000..#1FFF TI (Timex Interface) ROM (4KB, two times)
#2000..#3FFF TI RAM (1KB eight times or 2KB four times)
(1) TI (Timex Interface) with double sided PCB painted at the bottom on the green, without any numbers, at the bottom (lower side) at the center the "SER" sign.
Components : (IC1)TMM2016 (RAM), (IC2)D2732D (ROM), (IC5)SN74LS273N (output line driver), (IC6)HD74LS244P (input line driver), (C1)473/50V, (C2)ASE4832ZIB, (D1)1N4148R, (R1)680ohm 5%, miscroswitch black, edge connector ZX, and DA15M connector.
Rewired connections under PAL components.
In the DA15M pins 7 and 8 are not connected. Mask of the connector : %11001111, Bits 4 and 5 are not connected to 244 and 273 - the reading state is not known. (it is recommended - to connect them to the unused 244 outputs, and the corresponding 244 inputs - to the ground)
(2) TI with double sided glass laminate, yellow color, without numbers, and the visible manufacturer signs, the side holes are circular.
Elements : TMM2016, D2732D, SN74LS273N, SN74LS244N, (2x)+2.2/+25V(C), 22uF/25V,DA9C38(T), microswitch white, edge connector ZX to the soldering, DA15M.
Unused inputs 244 and 273 are connected to the ground thru wires.
In the DA15M pins 7 and 8 not connected and cut. Mask of the connector: %11001111.
Bits 4 and 5 connected thru wires to 244 - low state when read.
GAL (PAL,PALCE) chips 16V8 are connected so:
__
__
__ __
-\
CLK Io \/ |
+5V
A12 Io \/ | +5V /-
| A14 I I
/L3 /IORQ
I O /IN |F
Z| A13 I O
CLK
/RD I I
A0 |D
X|
A10 I I
A15
A8 I I
/WR |D
|
A9 I IC3 O
/ROM A11
I IC4 | nc (A1) |
B|
A3 I O
/RAM
A7 I O
/L3 |3
u|
A2 I I
/L2
A6 I O
/L2 |0
s| /MREQ
I O
/L1
A5 I I
/L1 |0
|
/M1 I O
ZXDIS A4
I O /OUT |0
-/ GND |______I
GND
GND |______I A1 \-
: A0..A15, /IORQ, /M1, /MREQ, /RD, /WR
Power:
GND, +5V
TI sterring: /IN - read from port #EF (74244, pin 1 19)
/OUT - write to port #EF (74273, pin 11)
/RAM - activate TI RAM (2016, pin 18 & 20)
/ROM - activate TI ROM (2732D, pin 18 & 20)
ZX sterring: ZXDIS - thru 680om to +5V, thru diode to /ROMCS (or to the transistor base in the same purpose)
local connections : CLK, /L1, /L2, /L3
Other :
nc - not connected inside the chip.
Direction, purpose, and polarisation of CLK, /L1, /L2, /L3 signals are taken freely, and can vary between particular versions. This doesn't matter, as long both PAL's are programmed together (they must cooperate).
IC3 signals:
ZXDIS := /A9
(high state on the D of the latch only for adresses which disconnects ZX ROM : #0000 and
#0008 - in real life (CLK signal coding) /A9 is enough.)
L1 = A2 * A3
(output inverted - low state on /L1 for the
#xxEF port adress)
RAM = ZXDIS * A13 * /A14 * /A15 * MREQ
(output inverted - low state on /RAM, if ZX ROM is disconnected and memory #2000..#3FFF adressed)
ROM = ZXDIS * /A13 * /A14 * /A15 * MREQ * RD
(output inverted - low state on /ROM if ZX ROM is disconnected and memory #0000..#1FFF is addressed for reading)
CLK = L2 * /A3 * /A9 * /A10 * /A13 * /A14 * /A15 * MREQ * M1
+ L3 * /A2 * /A3 * A9 * A10 * /A13 * /A14 * /A15 * MREQ * M1
(high state for the instruction getting from addresses switching ZX ROM)
IC4 signals:
OUT = L1 * A0 * A1 * /A4 * A5 * A6 * A7 * IORQ * WR
(output inverted - low state on /OUT for #xxEF port address for writing)
L2 = /A0 * /A1 * /A4 * /A5 * /A6 * /A7 * /A8 * /A11 * /A12
(output inverted - low state on /L2 for #0000 and #0008)
L3 = /A0 * A1 * /A4 * /A5 * /A6 * /A7 * /A8 * /A11 * /A12
(output inverted - low state on /L3 for address #0604)
IN = L1 * A0 * A1 * /A4 * A5 * A6 * A7 * IORQ * RD
(output inverted - low state on /IN for #EF port address for reading)
"output inverted" in the description means a lack of signal negation on the XOR gate, done by bits SL1n=0
The type of connection should be checked with the above description. All modifications should be made on the circit board(PCB).
Timex FDD with ZX Spectrum 128K (Plus/Plus 2/Plus 3/Plus 2A/B)
The Timex FDD can work with the 128K versions of the ZX Spectrum. To use the Timex FDD the ROM in the FDD Interface must be replaced, because a part of ROM1 is used to reset the Spectrum. When the 128K code is taken from ROM0, the computer crashes.
So for the 128K and 128K+2, the FDD Interface must perform an OUT #7FFD, #10 before initialization. This change was made by STAVI in Poland. To work with the ZX Spectrum 128K Plus 3, except the /ROMCS fix, an OUT #1FFD,#04 must be performed.